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www.irf.com ? 2009 international rectifier 23 july 7, 2009 IRS2552D ccfl/eefl ballast controller ic features ? drives up to two igbt/mosfet power devices ? integrated programmable oscillator ? soft start function ? 15.6 v voltage clamp on v cc ? micro-power startup ? 0 v to 5 v input analog dimming ? programmable ignition frequency ? programmable ignition time ? lamp current control ? programmable deadtime ? supports multi-lamp operation ? burst dimming with soft start at every burst ? latched open circuit protection ? integrated bootstrap functionality ? excellent latch immunity on all inputs & outputs ? integrated esd protection on all pins typical application ? ccfl/eefl inverter product summary topology half-bridge v offset 600 v v out v cc i o+ & i o- (typical) 300 ma & 450 ma deadtime (programmable) 500ns ~ 2s package options 16-lead pdip 16-lead soic (narrow body) typical application diagram www..net
IRS2552D www.irf.com ? 2009 international rectifier 2 table of contents page typical application diagram 1 qualification information 4 absolute maximum ratings 5 recommended operating conditions 6 electrical characteristics 7 functional block diagram 10 lead definitions 12 lead assignments 13 state diagram 14 application information and additional details 15 package details 29 part marking information 30 ordering information 32 www..net
IRS2552D www.irf.com ? 2009 international rectifier 3 description the IRS2552D incorporates a high voltage half-bridge gate dr iver with a front end that incorporates full control functionality for ccfl/eefl ballasts. includes a progr ammable ignition and supports dimming via analog or pwm control voltage. hvic and latch immune cmos tec hnologies enable ruggedized monolithic construction. the output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. noise immunity is achieved with low di/dt peak of the gate drivers, and with an undervolt age lockout hysteresis of approximately 1 v. the IRS2552D also includes protection f eatures for over-current and over-voltage of the lamps. www..net
IRS2552D www.irf.com ? 2009 international rectifier 4 qualification information ? industrial ?? (per jedec jesd 47e) qualification level comments: this family of ics has passed jedec?s industrial qualification. ir?s consumer qualification level is granted by extension of t he higher industrial level. soic16 msl3 ??? (per ipc/jedec j-std-020c) moisture sensitivity level pdip16 not applicable (non-surface mount package style) machine model class c (per jedec standard eia/jesd22-a115-a) esd human body model class 3a (per eia/jedec standard jesd22-a114-b) ic latch-up test class i, level a (per jesd78a) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales repr esentative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repr esentative for further information. www..net
IRS2552D www.irf.com ? 2009 international rectifier 5 absolute maximum ratings absolute maximum ratings indicate sustained limits bey ond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all cu rrents are defined positive into any lead. the thermal resistance and power dissipation ratings are m easured under board mounted and still air conditions. symbol definition min. max. units v b high-side floating supply voltage -0.3 625 v s high-side floating supply offset voltage v b - 25 v b + 0.3 v h high-side floating output voltage v s ? 0.3 v b + 0.3 v l low-side output voltage -0.3 v cc + 0.3 v co vco pin voltage -0.3 v cc + 0.3 v ct c t pin voltage -0.3 v cc + 0.3 v dt dt pin voltage -0.3 v cc + 0.3 min min pin voltage -0.3 v cc + 0.3 dim dim pin voltage -0.3 v cc + 0.3 cr cr pin voltage -0.3 v cc + 0.3 cd cd pin voltage -0.3 v cc + 0.3 sd sd pin voltage -0.3 v cc + 0.3 cs cs pin voltage -0.3 v cc + 0.3 v i cc supply current ? --- 25 ma dv s /dt allowable offset voltage slew rate -50 50 v/ns 16l-pdip --- 1.3 p d package power dissipation @ t a +25 oc 16l-soic --- 1.4 w 16l-pdip --- 70 r ja thermal resistance, junction to ambient 16l-soic --- 82 oc/w t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) --- 300 oc ? this ic contains a voltage clam p structure between the chip v cc and com which has a nominal breakdown voltage of 15.6 v. please note that this supply pin s hould not be driven by a dc, low impedance power source greater than the v clamp specified in the electrical characteristics section. www..net
IRS2552D www.irf.com ? 2009 international rectifier 6 recommended operating conditions for proper operation the device should be used within the recommended conditions. symbol definition min. max. units v bs high-side floating supply voltage v cc ? 0.7 v clamp v s steady-state high-side floating supply offset voltage -3.0 ? 600 v cc supply voltage v ccuv+ +0.1v v clamp v i cc supply current ?? 10 ma t j junction temperature -40 125 oc ? care should be taken to avoid output switching conditions where the v s node flies inductively below ground by more than 5 v. ?? enough current should be supplied to the v cc pin of the ic to keep the internal 15.6 v zener diode clamping the voltage at this pin. recommended component values symbol component min. max. units r min min pin resistor value 5 r max max pin resistor value 5 r dt dt pin resistor value 22 --- k c t ct pin capacitor value 330 c dt dt pin capacitor value 47 --- pf c r cr pin capacitor value 1 c d cd pin capacitor value 1 --- nf www..net
IRS2552D www.irf.com ? 2009 international rectifier 7 electrical characteristics v bias (v cc , v bs ) = 14 v, c t = 1 nf and t a = 25 c unless otherwise specified. the input parameters are referenced to com. the v o and i o parameters are referenced to com and are applic able to the respective output leads: ho or lo. symbol definition min typ max units test conditions low voltage supply characteristics v ccuv + rising v cc undervoltage lockout threshold 9.5 10.5 11.5 v ccuv - falling v cc undervoltage lockout threshold 8.5 9.5 10.5 v ccuvhys v cc undervoltage lockout hysteresis 0.5 1 1.5 v n/a i qccuv micropower startup v cc supply current --- 300 350 a v cc = v ccuv+ -100 mv rising i qcc quiescent v cc supply current --- 4.0 4.5 r min = 12 k , run mode ct = 0 v i qccflt v cc supply current --- 0.9 1.3 fault mode i cc,fmin v cc current @ f osc = fmin --- 4.7 5.3 ma r min = 12 k , run mode v clamp v cc clamp voltage 14.6 15.6 16.6 v i cc = 19 ma floating supply characteristics i qbsuv micropower startup v bs supply current --- 6 20 v cc v ccuv- , v cc = v bs i bs v bs supply current --- 1000 1200 a ho oscillating v bsuv+ v bs supply undervoltage positive going threshold 6.5 7.5 8.5 v bsuv- v bs supply undervoltage negative going threshold 6.0 7.0 8.0 v n/a i lk offset supply leakage current --- --- 50 a v b = v s = 600 v oscillator i/o characteristics f min minimum oscillator frequency 36.5 39 42.5 r min = 12 k , run mode f max maximum oscillator frequency 67 69 71 khz r max = 6.8 k , ignition mode v ct+ upper ct ramp voltage threshold 4.8 5.0 5.2 v ct- lower ct ramp voltage threshold --- 0 --- v n/a i ct ct pin source current 350 410 470 a r min =12 k , run mode v min vmin pin voltage 4.8 5.0 5.2 v max vmax pin voltage 4.8 5.0 5.2 v min,flt vmin voltage in fault mode --- 0 --- v max,flt vmax voltage in fault mode --- 0 --- v n/a www..net
IRS2552D www.irf.com ? 2009 international rectifier 8 electrical characteristics v bias (v cc , v bs ) = 14 v, c t = 1 nf and t a = 25 c unless otherwise specified. the input parameters are referenced to com. the v o and i o parameters are referenced to com and are applic able to the respective output leads: ho or lo. symbol definition min typ max units test conditions ignition i cr,ign source current at cr pin in ign mode 3.7 4.5 5.3 a r min = 12 k , ignition mode v cs,ign ignition detection threshold 0.57 0.6 0.63 v n/a gate driver output characteristics v oh high-level output voltage, v bias ? v o --- v cc --- v v ol low-level output voltage, v o --- com --- i o = 0 a v ol,uv uv-mode output voltage, v o --- com --- mv i o = 0 a, v cc v ccuv- t r output rise time --- 80 150 t f output fall time --- 45 100 ns n/a t d output deadtime (ho or lo) 1.0 1.1 1.2 s r dt = 2.2 k , c dt = 1 nf i o+ output source current --- 300 --- i o- output sink current --- 450 --- ma n/a bootstrap fet characteristics v b,on v b when the bootstrap fet is on 13.2 13.5 --- v n/a i b,cap v b source current when fet is on 40 55 --- ma c bs = 0.1 f i b,10v v b source current when fet is on 9 12 --- ma v b = 10 v shutdown v sd , th shutdown threshold at sd pin 1.9 2.0 2.1 v n/a i cd,source cd pin source current 3.7 4.5 5.3 a v sd >v sd,th , r min = 12 k v cd,th threshold at which cd triggers shutdown 4.8 5.0 5.2 v v cc = 14 v www..net
IRS2552D www.irf.com ? 2009 international rectifier 9 electrical characteristics v bias (v cc , v bs ) = 14 v, c t = 1 nf and t a = 25 c unless otherwise specif ied. the input parameters are referenced to com. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. symbol definition min typ max units test conditions over-current compensation v cs,th current compensation threshold at cs pin 1.15 1.21 1.27 v n/a i cd,oc source current at cd pin when the ic is in current compensation mode 3.7 4.5 5.3 a v cs >v cs,th , r min = 12 k v cd,oc voltage on cd where duty cycle reaches minimum 4.8 5.0 5.2 v n/a dc min minimum ho duty cycle --- 10% --- --- v cd = 4.7 v, run mode dimming v cr+ cr pin upper threshold voltage 4.8 5.0 5.2 v cr- cr pin lower threshold voltage --- 0.2 --- v n/a i cr,run source current at cr pin in run mode 125 150 175 a r min = 12 k f cr frequency at cr pin 240 310 370 hz c r = 100 nf, run mode, r min = 12 k soft start dc min minimum ho duty cycle --- 10% --- --- v cr = 0 v, v dim < v dim,ss v cr,ss end of soft start voltage 0.88 0.96 1.04 v dim < v dim,ss v dim,ss soft start disable threshold --- 4.8 --- v n/a enable v enath enable threshold 1.9 2.2 2.5 v v enahys enable hysteresis --- 200 --- mv n/a www..net
IRS2552D www.irf.com ? 2009 international rectifier 10 functional block diagram q s r q 3 ct 8 ena 11 sd 6 max 7 dim 12 cs 5 min 0.6v 4 dt 10 cd 9 cr q s r2 q r1 imin 5v 5v 0v icd 2.2v 2v 1.21v uv 5v imax uvlo uv 0.2v 5v icr_ign icr_run band gap ref 5v vbg ignition logic soft start control over current control dead time control duty cycle control output logic 1 13 2 com lo vcc 15.6v 15 16 14 vs ho vb level shift pulse filter & latch boot strap drive en 5v en www..net
IRS2552D www.irf.com ? 2009 international rectifier 11 input/output pin equivalent circuit diagrams: IRS2552D vcc com lo esd diode esd diode vb vs ho esd diode esd diode 25v 25v 600v vcc com ct esd diode esd diode r esd r esd vcc com min, max esd diode esd diode r esd www..net
IRS2552D www.irf.com ? 2009 international rectifier 12 lead definitions symbol description vcc logic and internal gate drive supply voltage com ic power and signal ground ct oscillator timing capacitor dt independent dead time r and c min rfmin sets running frequency max rfmax sets ignition mode frequency dim 0 to 5 v dc burst mode dimming control input ena chip enable (2 v logic threshold) cr burst dimming ramp cd shutdown delay timing sd open load detection cs ignition detection (0.6 v threshold) , over-current (1.2 v threshold) lo low side output vs half bridge ho high side output vb high side floating supply www..net
IRS2552D www.irf.com ? 2009 international rectifier 13 lead assignments 16 15 14 13 12 11 10 1 2 3 4 5 6 7 i r s 2 5 5 2 d vcc ct min max dt ena vb ho vs sd cs cd com lo 8 9 dim cr www..net
IRS2552D www.irf.com ? 2009 international rectifier 14 state diagram ? ? all values are typical. applies to application circuit on page 1. www..net
IRS2552D www.irf.com ? 2009 international rectifier 15 application information and additional details information regarding the following topics is included as subsections within this section of the datasheet. ? igbt/mosfet gate drive ? undervoltage lockout protection ? oscillator ? deadtime ? ignition ? run mode ? lamp current control ? frequency, current and deadtime calculation ? dimming function ? soft start ? pcb layout tips ? additional documentation igbt/mosfet gate drive the IRS2552D hvics are designed to drive up to two mosfet or igbt power devices. figures 1 and 2 illustrate several parameters associated with the gat e drive functionality of the hvic. t he output current of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the high-side power switch and v lo for the low-side power switch; this parameter is sometimes generically called v out and in this case does not differentiate betw een the high-side or low-side output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + - figure 1: hvic sourcing current figure 2: hvic sinking current undervoltage lock-out the IRS2552D includes an under voltage lockout circuit su ch that it remains in micro-power mode until the voltage at vcc pin exceeds the v ccuv+ threshold. when v cc exceeds the v ccuv+ threshold the IRS2552D oscillator starts up and gate drive signals appear at t he lo and ho outputs, provided the enable pin is connected to a voltage source above v enath . the lo output will always go high first in order to pre-charge the bootstrap capacitor before the ir s2552d begins normal operation. www..net
IRS2552D www.irf.com ? 2009 international rectifier 16 oscillator during uvlo and shutdown and the voltage at the min and max pins remain at 0 v. when v cc is raised above v ccuv+ the oscillator will start and lo and ho will produce output drive waveforms at frequency f max . the max pin sources 5 v and the resistance connected fr om this point to com determines the c t charging current and consequently the frequency. r min is always connected from the min pin to com, which sets the run mode frequency. in ignition mode the max pin supplies 5 v to r max , which is connected to com setting a higher c t charging current and consequently a higher ignition frequency, as r max is smaller than r min . in run mode the max pin is no longer active and the voltage will drop to 0v. c t charges until the voltage reaches the 5 v threshold and then it is discharged rapidly to v ct- . it then begins to charge again, repeating this sequence and producing a saw tooth waveform. the min pin sour ces 5 v during ignition and run modes. the current flowing through f min to com determines the charging current of c t during run mode and also serves as a current reference for the currents supplied from the cd and cr pins. vcc vccuv+ ct vct+ vct- dt 1/3*vcc lo ho figure 3: oscillator waveforms deadtime in the IRS2552D the dead time is determined by an independent external timing circuit comprising of r dt and c dt and is not affected by the values of c t , r min or r max . the dt pin voltage is held at com when lo or ho is high. c dt is charged through r dt , which is connected to vcc, when dt is internally disconnected from com at the start of the dead time. the dead time ends when c dt has charged to 1/3 v cc . this allows the dead time to remain consistent over the working range of v cc , i.e. from uvlo+ to the clamp voltage of 15.6 v. ignition during the ignition phase the c r capacitor is charged through an internal current source icr_ign. when c r reaches v cr+ then if the voltage at cs is greater than vcs ign , the IRS2552D will enter run mode. if the voltage at the cs pin is less than vcs ign the IRS2552D will enter fault mode whereby lo and ho will both go low and the IRS2552D will shut down until v cc is reduced below v ccuv- and then increased above v ccu+ . the ignition function is achieved by applying a frequency somewhat above resonance to the output step up transformer and resonant load. this should develop sufficient voltage acro ss the lamps to allow partial ignition and some arc current to flow. the combined lamp current is fed back to the cs pin through a suitable isolating network to determine whether the lamps have ignit ed successfully. if a successful igniti on is detected after the voltage at c r has reached v cr+ then r max is disconnected inside the IRS2552D and t he frequency will switch immediately to www..net
IRS2552D www.irf.com ? 2009 international rectifier 17 to f min , therefore applying maximum power to the lamps. at this point the burst mode dimming function will be enabled. run mode in run mode an additional current source icr_run is al so switched into the circuit. this causes c r to ramp up to v cr+ much more rapidly than before. the c r pin is used to provide ignition timing as well as the burst mode dimming low frequency ramp. if the output is open circuit a very large voltage develops at the output. this is fed back to the sd pin through some suitable isolated sensing network such that the voltage at the sd pin will exceed vsdth during an over- voltage condition. at this stage the capacitor c d begins to charge through a current source. when vsd > vsdth the burst mode dimming function is disabled and the output will be continuous. if the voltage at sd drops bel ow vsdth the capacitor c d will be discharged to 0v again. if sd remains above vsdth long enough for the c d capacitor voltage to reach vcdmax or about 5 v then the IRS2552D will shut down and go into fault mode. lamp current control additionally the half bridge current is monitored at the cs pin so that during running if too much power is supplied to the lamps the IRS2552D is able to com pensate by reducing the oscillator duty cycle while maintaining the same run frequency. this prevents t he lamps from being over driven preventing premature end of life. when vcs > vcsth the c d capacitor will begin to charge and the cd pin voltage will rise. as this occurs the duty cycle will begin to adjust, i.e. the ho on time will become gradually shorter and the lo on time will become gradually longer. the dead time will remain constant at all times. in this way the power to the output will be reduced while the frequency remains at f min . as the cd voltage rises, the dut y cycle will be further reduced. if vcs then drops below vcsth then the duty cycle will be regulated at that point and thus the current will be maintained at this limit. if vcs remains above vc sth then the voltage will continue to rise on c d until it reaches vcdmax, at which point the duty cy cle reaches its minimum limit dc min and the IRS2552D will enter fault mode, requiring v cc to fall below uvlo- and then rise above uvlo+ in order to re-start. frequency, current, and dead time calculation the running frequency of the IRS2552D is given by the following formula: min t min r c f ? ? = 09 . 2 1 where v min = 5 v, i.e. when the ignition ramp is complete and r max has no further effect on the oscillator. the ignition frequency given by: max t max r c f ? ? = 09 . 2 1 and the dead time is calculated by: ) 5 . 1 ln( ? ? = dt dt dt c r t dt dt dt c r t ? ? = 405 . 0 www..net
IRS2552D www.irf.com ? 2009 international rectifier 18 maximum duty cycle ) * ( 5 . 0 f t dc dt max ? = the icr charging current during ignition mode and the icd charging current are given by: min ign r icr 06 . 0 = min r icd 06 . 0 = the icr charging current and frequency during run mode are given by: min run r icr 8 . 1 = cr min cr c r f ? = 36 . 0 dimming function the IRS2552D supports burst mode dimming, meaning that t he output drive to the lamps is pulsed on and off at a low frequency and the burst duty cycle is adjusted to c ontrol the average current and therefore the light output of the lamps. the IRS2552D contains a low frequency osc illator that generates a ramp waveform at the cr pin from 0 v to 5 v. the ramp frequency is dependent on the value of the external c r capacitor. a dc dimming control voltage is fed into the dim pin which is com pared with the dimming ramp by means of an internal comparator, which generates the pwm signal that is used internally to switch the outputs on and off. thus when the dim voltage is at 5 v the outputs will be on all of the time and when it is at 0 v the outputs will be off all of the time. alternatively a pwm dimming control signal from 0 v to 5 v can be fed directly into the dim pin to allow external pwm control independent of the dimming ramp. during the off period the lo and ho outputs are both low. www..net
IRS2552D www.irf.com ? 2009 international rectifier 19 lo ho 5v 0.2v dim cr 1v soft start soft start soft start duty cycle increases from 10% to 50% figure 4: dimming waveform soft start on off dc increases from dc min to dc max dc=dcmax dc=0 vdim vdim vcrss vdim vdim>vdimss vcr vdim run mode iccrun charges cr up to vcr+. cr oscillates at fcr (sawtooth) half-bridge oscillates at fmin. vdc reset to 0v soft start in addition the IRS2552D includes a soft start function t hat operates at the start of each burst, during dimming operation when vdim < vdim ss . the soft start will operate during the portion of the dimming ramp cr at the start of each burst from cr = 0 v to cr = vcr ss . when vcr = 0 the duty cycle will be at minimum (dcmin) and will linearly increase to 50% (minus the dead time) when vcr reaches vcr ss . this function is enabled only in run mode and allows inrush currents to be eliminated duri ng burst mode dimming, while always maintaining the frequency at f min . www..net
IRS2552D www.irf.com ? 2009 international rectifier 20 pcb layout tips distance between high and low voltage components: it?s strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. ground plane: in order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 5). in order to reduce the em coupling and improve the power sw itch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector- to-gate parasitic capacitance. the par asitic auto-inductance of the gate l oop contributes to developing a voltage across the gate-emitter, thus increasing t he possibility of a self turn-on effect. figure 5: antenna loops supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and v ss pins. a ceramic 1 f ceramic capacitor is suitable for most applications. this component should be placed as close as possible to the pins in order to reduce parasitic elements. routing and placement: power stage pcb parasitic elements can cont ribute to large negative voltage transients as the switch node; it is recommended to limit the phase voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray induc tance. however, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. this includes placing a resistor (5 ? or less) between the v s pin and the switch node (see figure 6), and in some cases using a clamping diode between v ss and v s (see figure 7). see dt04-4 at www.irf.com for more detailed information. www..net
IRS2552D www.irf.com ? 2009 international rectifier 21 figure 6: v s resistor figure 7: v s clamping diode additional documentation several technical documents related to the use of hvics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these documents. dt97-3: managing transients in control ic driven power stages an-1123: bootstrap network analysis: focusi ng on the integrated bootstrap functionality dt04-4: using monolithic high voltage gate drivers an-978: hv floating mos-gate driver ics www..net
IRS2552D www.irf.com ? 2009 international rectifier 22 programmable parameter characteristics figure 7 to 12 provide the characteristics of the progr ammable parameters as a function of the value of the p ro g rammin g com p onents. 0 10 20 30 40 50 60 70 80 90 100 0 300 600 900 1200 1500 ct( pf) fmin, fmax(kh z rmin, rmax=12.1k 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 rmin( k ) fmin(khz fi g ure 7: fmin , fmax vs. ct fi g ure 8: fmin vs. rmin 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 rma x( k ) fmax(khz ) 0 400 800 1200 1600 2000 0 400 800 1200 1600 2000 cdt( pf) dt(ns) rdt=2.21k figure 9: fmax vs. rmax figure 10: dt vs. cdt 0 500 1000 1500 2000 2500 3000 01234567 rdt( k ) dt(ns) 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 2500 3000 3500 cr( pf) fcr(khz ) figure 11: dt vs. rdt figure 12: fcr vs. cr www..net
www.irf.com ? 2009 international rectifier 23 parameter characteristics figure 13 to 18 provide the characteristics of the main parameters as a function of vcc or the oscillator frequency 0 4 8 12 16 20 0 2 4 6 8 10 12 14 16 v cc( v ) iqcc(ma ) 0 1 2 3 4 5 6 9 9.2 9.4 9.6 9.8 10 10.2 vcc(v) iqcc(ma ) figure 13: icc vs. vcc figure 14: iqcc vs. vcc (vcc raising and falling 0 10 20 30 40 50 60 70 80 10 11 12 13 14 15 16 vcc(v) frequency(khz ) rmin=12.1k, rnax=6.81k fmax fmin 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 10 11 12 13 14 15 16 vcc(v) tdead(us ) figure15: fmin, fmax vs. vcc figure 16: td vs. vcc 0 1 2 3 4 5 6 7 8 9 10 30 34 38 42 46 50 fmin(khz ) icc_run(m a 0 1 2 3 4 5 6 7 8 9 10 30 34 38 42 46 50 fma x( khz ) icc_fmax(ma ) fi g ure 17: icc run vs. fmin fi g ure 18: icc fmax vs. fma x www..net
IRS2552D www.irf.com ? 2009 international rectifier 24 parameter temperature trends figures 38-58 provide the characteristics of the main par ameters over temperature based on three temperatures (- 40 oc, 25 oc, and 125 oc) average testing. 8.5 9 9.5 10 10.5 11 11.5 -50 -25 0 25 50 75 100 125 temperature (c) vccuv ( v) vccuv+ vccuv- 0 50 100 150 200 250 300 350 -50 -25 0 25 50 75 100 125 temperature (c) iqccuv (ua) figure 19: vccuv vs. temperature figure 20: iqccuv vs. temperature 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 -50 -25 0 25 50 75 100 125 temperature (c) iqcc (ma) 3 3.5 4 4.5 5 5.5 -50 -25 0 25 50 75 100 125 temperature (c) icc,fmin (ma) figure 21: iqcc vs. temperature figure 22: icc,fmin vs. temperature www..net
IRS2552D www.irf.com ? 2009 international rectifier 25 14.6 15.1 15.6 16.1 16.6 -50 -25 0 25 50 75 100 125 temperature (c) vclamp ( v) 6 6.5 7 7.5 8 8.5 -50 -25 0 25 50 75 100 125 temperature (c) vbsuv ( v) vbsuv+ vbsuv- figure 23: vclamp vs. temperature figure 24: vbsuv vs. temperature 36.5 37.5 38.5 39.5 40.5 41.5 42.5 -50 -25 0 25 50 75 100 125 temperature (c) fmin (khz) 67 67.5 68 68.5 69 69.5 70 70.5 71 -50 -25 0 25 50 75 100 125 temperature (c) fmax (khz) figure 25: fmin vs. temperature figure 26: fmax vs. temperature 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 -50 -25 0 25 50 75 100 125 temperature (c) vmin ( v) 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 -50 -25 0 25 50 75 100 125 temperature (c) vmax ( v) figure 27: v min vs. temperature figure 28: vmax vs. temperature www..net
IRS2552D www.irf.com ? 2009 international rectifier 26 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 -50 -25 0 25 50 75 100 125 temperature (c) icr_ign (ua) 570 580 590 600 610 620 630 -50 -25 0 25 50 75 100 125 temperature (c) vcs,ign (mv) figure 29: i cr,ign vs. temperature figure 30: v cs,ign vs. temperature 1 1.02 1.04 1.06 1.08 1.1 1.12 1.14 1.16 1.18 1.2 -50 -25 0 25 50 75 100 125 temperature (c) dt (us) 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 14 -50 -25 0 25 50 75 100 125 temperature (c) vb,on ( v) figure 31: t d vs. temperature figure 32: v b,on vs. temperature 0 10 20 30 40 50 60 70 80 90 -50-25 0 255075100125 temperature (c) ib,cap (ma) 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 temperature (c) ib,10v (ma) figure 33: i b,cap vs. temperature figure 34: i b,10v vs. temperature www..net
IRS2552D www.irf.com ? 2009 international rectifier 27 1.9 1.95 2 2.05 2.1 -50 -25 0 25 50 75 100 125 temperature (c) vsdth ( v) 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 -50 -25 0 25 50 75 100 125 temperature (c) icd,source (ua) figure 35: v sd,th vs. temperature figure 36: v cd,source vs. temperature 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 -50 -25 0 25 50 75 100 125 temperature (c) vcdth ( v) 1.15 1.17 1.19 1.21 1.23 1.25 1.27 -50 -25 0 25 50 75 100 125 temperature (c) vcsth ( v) figure 37: v cd,th vs. temperature figure 38: v cdsth vs. temperature 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 -50 -25 0 25 50 75 100 125 temperature (c) icd,oc (ua) 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 -50 -25 0 25 50 75 100 125 temperature (c) vcd,oc ( v) figure 39: i cd,oc vs. temperature figure 40: v cd,oc vs. temperature www..net
IRS2552D www.irf.com ? 2009 international rectifier 28 0 2 4 6 8 10 12 14 -50-25 0 255075100125 temperature (c) dcmin ( %) 240 260 280 300 320 340 360 -50 -25 0 25 50 75 100 125 temperature (c) fcr ( z) figure 41: dc min vs. temperature figure 42: f cr vs. temperature 880 900 920 940 960 980 1000 1020 1040 -50 -25 0 25 50 75 100 125 temperature (c) vcr_ss (mv) 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 5 -50 -25 0 25 50 75 100 125 temperature (c) vdim_ss ( v) figure 43: v cr,ss vs. temperature figure 44: v dim,ss vs. temperature 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 -50 -25 0 25 50 75 100 125 temperature (c) enath ( v) enath+ enath- 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 -50 -25 0 25 50 75 100 125 temperature (c) iqbs (ma) figure 45: v ena vs. temperature figure 46: ibs vs. temperature www..net
IRS2552D www.irf.com ? 2009 international rectifier 29 package details: pdip16 and s016n www..net
IRS2552D www.irf.com ? 2009 international rectifier 30 package details: soic16n, tape and reel carrier tape dimension for 16soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 6.40 6.60 0.252 0.260 f 10.20 10.40 0.402 0.409 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 16soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c www..net
IRS2552D www.irf.com ? 2009 international rectifier 31 part marking information www..net
IRS2552D www.irf.com ? 2009 international rectifier 32 ordering information standard pack base part number package type form quantity complete part number pdip16 tube/bulk 25 IRS2552Dpbf tube/bulk 45 IRS2552Dspbf IRS2552D soic16n tape and reel 2500 IRS2552Dstrpbf the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this inform ation. international rectifier assumes no responsibility for any infringement of pat ents or of other rights of third parties which may result from the use of this in formation. no license is granted by implication or otherwise u nder any patent or patent rights of international rectifier. the specifications mentioned in this doc ument are subject to change without notice. this document supersedes and replaces all inform ation previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 www..net

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